Description

Hardware accelerators of various kinds offer a potential for achieving massive performance in applications that can leverage their high degree of parallelism and customization. Examples include graphics processors (GPUs), manycore co-processors, as well as more customizable devices, such as FPGA-based systems, and streaming data-flow architectures.

The research challenge for this topic is to explore new directions for actually realizing this potential. We encourage submissions in all areas related to accelerators: architectures, algorithms, languages, compilers, libraries, runtime systems, coordination of accelerators and CPU, and debugging and profiling tools. Application-related submissions that contribute new insights into fundamental problems or solution approaches in this domain are welcome as well, including big data, data analytics, and computational science/engineering.

Focus

• New accelerator architectures
• Programming models, languages, compilers, and runtime environments for accelerators
• Tools for debugging, profiling, and optimizing programs on accelerators
• Hybrid and heterogeneous computing mixing several, possibly different types of accelerators, and/or CPUs
• Parallel algorithms and applications for accelerators, even beyond what is considered suitable for current accelerator architectures
• Performance modeling and benchmarks for accelerators
• Library support for accelerators
• Power-aware/energy efficient solutions for accelerators